unisonic technologies co., ltd ucd4015 cmos ic www.unisonic.com.tw 1 of 8 copyright ? 2013 unisonic technologies co., ltd qw-r502-875.a cmos dual 4-stage static shift register ? description ucd4015 consists of two identical,independent,4-stage serial-input/parallel-output r egisters. each register has independent clock and reset input as well as a single serial data input. ?q? outputs are avai lable from each of the four stages on both registers. a ll registers stages are d-type, master-slave flip-flops. the logic level present at the data input is transferred into the first register stage and shifted over one stage at each positive-going clo ck transition. resetting of all stages is accomplished by a high level on the reset line. register expansion to 8 stages using one ucd4015 package or to more than 8 stages using additional ucd4015?s is possible. ? features * 12mhz (typ.) clock rate at 10v * maximum input current of 1 a at 18v * fully static operation * 8 master-slave flip-flops plus input and output buffering ? applications * general-purpose register * serial-input/parallel-output data queueing * serial to parallel data conversion sop-16 tssop-16 ? ordering information ordering number package packing lead free halogen free ucd4015l-s16-t ucd4015g-s16-t sop-16 tube ucd4015l-s16-r ucd4015g-s16-r sop-16 tape reel ucd4015l-p16-t ucd4015g-p16-t tssop-16 tube ucd4015l-p16-r UCD4015G-P16-R tssop-16 tape reel
ucd4015 cmos ic unisonic technologies co., ltd 2 of 8 www.unisonic.com.tw qw-r502-875.a ? pin configuration ? logic diagram
ucd4015 cmos ic unisonic technologies co., ltd 3 of 8 www.unisonic.com.tw qw-r502-875.a ? true table c l d r q 1 q n 0 0 0 q n-1 1 0 1 q n-1 x x 1 0 0 x 0 q 1 q n (nc) note: x = don?t care case, nc = no change
ucd4015 cmos ic unisonic technologies co., ltd 4 of 8 www.unisonic.com.tw qw-r502-875.a ? absolute maximum rating (t a =25c , unless otherwise specified) parameter symbol ratings unit supply voltage v dd -0.5 ~ 20 v input voltage v in -0.5 ~ v cc + 0.5 v output voltage v out -0.5 ~ v cc + 0.5 v input clamp current (v in <0, or v in >v cc ) i ik 10 ma power dissipation t a =-40c~+85c p d 500 mw operating temperature t opr -40 ~ +125 c storage temperature t stg -65 ~ +150 c note: 1. the input and output voltage ratings may be exce eded if the input and output cu rrent ratings are observed. 2. absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. ? thermal data parameter symbol ratings unit junction to ambient sop-16 ja 73 c/w tssop-16 108 c/w ? recommended operating comditions parameter symbol conditions min typ max unit supply voltage v dd 3 18 v clock pulse width t w v dd =5v 180 ns v dd =10v 80 v dd =15v 50 clock frequency f cl v dd =5v 3 mhz v dd =10v 6 v dd =15v 8.5 clock rise and fall time t r , t f v dd =5v 15 s v dd =10v 6 v dd =15v 2 data set-up time t su v dd =5v 70 ns v dd =10v 40 v dd =15v 30 ? electrical characteristics (t a =25c , unless otherwise specified) parameter symbol test conditions min typ max unit quiescent supply current i dd v in =0, 5v, v dd =5v 0.04 5 a v in =0, 10v, v dd =10v 0.04 10 v in =0, 15v, v dd =15v 0.04 20 v in =0, 20v, v dd =20v 0.08 100 output low (sink) current i ol v out =0.4v, v dd =5v 0.51 1 ma v out =0.5v, v dd =10v 1.3 2.6 v out =1.5v, v dd =15v 3.4 6.8 output high (source) current i oh v out =4.6v, v dd =5v -0.51 -1 ma v out =2.5v, v dd =5v -1.6 -3.2 v out =9.5v, v dd =10v -1.3 -2.6 v out =13.5v, v dd =15v -3.4 -6.8 output voltage: low-level v ol v dd =5v 0 0.05 v v dd =10v 0 0.05 v dd =15v 0 0.05 output voltage: high-level v oh v dd =5v 4.95 5 v v dd =10v 9.95 10 v dd =15v 14.95 15
ucd4015 cmos ic unisonic technologies co., ltd 5 of 8 www.unisonic.com.tw qw-r502-875.a ? electrical characteristics(cont.) parameter symbol test conditions min typ max unit input low voltage v il v out =0.5, 4.5v, v dd =5v 1.5 v v out =1, 9v, v dd =10v 3 v out =1.5, 13.5v, v dd =15v 4 input high voltage v ih v out =0.5, 4.5v, v dd =5v 3.5 v v out =1, 9v, v dd =10v 7 v out =1.5, 13.5v, v dd =15v 11 input leakage current i i ( leak ) v in =0, 18v, v dd =18v 0.1 a ? switching characteristics (t a =25c, input t r , t f =20ns, c l =50pf, r l = 200k ? ) parameter symbol test conditions min typ max unit clocked operation propagation delay time t plh / t phl v dd =5v 160 320 ns v dd =10v 80 160 v dd =15v 60 120 transition time t thl / t tlh v dd =5v 100 200 ns v dd =10v 50 100 v dd =15v 40 80 maximum clock input frequency f cl v dd =5v 3 6 mhz v dd =10v 6 12 v dd =15v 8.5 17 minimum clock pulse width t wcl v dd =5v 90 180 ns v dd =10v 40 80 v dd =15 25 50 clock rise and fall time t rcl / t fcl v dd =5v 15 s v dd =10v 6 v dd =15v 2 minimum data setup time t su v dd =5v 35 70 ns v dd =10v 20 40 v dd =15v 15 30 minimum data hold timel t h v dd =5v 0 ns v dd =10v 0 v dd =15v 0 a verage input capacitance c i a ny input 5 7.5 pf reset operation propagation delay time t plh / t phl v dd =5v 200 400 ns v dd =10v 100 200 v dd =15v 80 160 minimum reset pulse width t wr v dd =5v 100 200 ns v dd =10v 40 80 v dd =15 30 60
ucd4015 cmos ic unisonic technologies co., ltd 6 of 8 www.unisonic.com.tw qw-r502-875.a ? test circuit and waveforms fig 1. test circuit inputs v m v load c l r l v in t r , t f v dd 20 ns v dd /2 v dd 50 pf 200 k ? v m v m v m v m v in 0v v oh v ol input output t plh t phl t plh t phl v oh v ol output v m v m 10% 90% t r 10% 90% t f 10% 90% t f 10% 90% t r notes: 1. c l includes probe and jig capacitance. 2. all input pulses are supplied by generator s having the following characteristics: prr 1mhz, z o = 50 ? .
ucd4015 cmos ic unisonic technologies co., ltd 7 of 8 www.unisonic.com.tw qw-r502-875.a ? test circuit and waveforms(cont.) 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 500 f 0.1uf v dd data c l c l c l c l c l c l i d fig4. dynamic power dissipation test circuit v ss inputs v ss v dd v dd i dd fig5. quiescent device current test circuit
ucd4015 cmos ic unisonic technologies co., ltd 8 of 8 www.unisonic.com.tw qw-r502-875.a ? test circuit and waveforms(cont.) fig6 input voltage test circuit fig7 input current test circuit note measure inputs sequentially, to both v dd and v ss ; connect all unused inputs to either v dd or v ss . utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
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